(a) Field of the Invention
The present invention relates to an integrated circuit structure and a layout design method thereof, and more particularly to an integrated circuit structure and a layout design method thereof which prearrange circuit passageways for reducing extent of modifying at future stage.
(b) Description of the Prior Arts
Along with the development of technologies, people further require features of communication products such as mobile phone or mobile products such as PDA to be lighter, thinner, shorter, and smaller so that applications of those integrated circuits (IC) satisfy with the above requirements are becoming broader and broader. Integrated circuit utilizes a way for three-dimensionizing a circuit to reduce the area used and can be frequently found in various applications.
Please refer to FIG. 1, which is a design flow chart of an integrated circuit. Just like software design, even if source coding is finished and is compiled by a compiler to be a run-able state, few programs can achieve designer's objects at its first running. First, a designer should design a circuit according to requirements and connects related elements layout to each other. Further, the circuit is simulated by aids of computers to find error connections or improper designs to be corrected. After affirming that no problem is existing and design objects are matched, the step of taping out is proceeded, wherein “tape out” means to deliver designed circuit to fab for production. Then, taking back the taped out product to perform practical test for verifying circuit characteristics of the chip. Afterwards, original circuit design is examined according to whether the test result matches to design objects. If there was mismatch or defect then backing to design steps for modifying. If design objects were matched then mass production can be performed according to the above taped out circuit.
However, the expense of modification for taped out product is very amazing. Please refer to FIG. 2, which is a schematic figure of conventional integrated circuit modification. The integrated circuit comprises a substrate 1, which forms many circuit elements such as FET and CMOS by semiconductor processes, pluralities of metal layers used as connection layout for circuit elements, and some isolation layers: the first isolation layer 31, the second isolation layer 32, the third isolation layer 33 and the fourth isolation layer 34, which are disposed among metal layers and providing electrical isolation among metal layers; that is to say one metal layer is not conducted with another metal layer. Usually, one terminal of the above-mentioned circuit element is pulled to the first metal layer 21 for usage of circuit layout. Since consumers require more and more functions, designed circuit becomes larger and larger and frequently contains millions of circuit elements. Thus, the circuit elements are not probably accomplished one by one manually. For accelerating the design flow, usually a method of “modulization” is utilized, i.e. elements with frequently-used functions are assembled previously to a fixed form which can be used directly at design stage without designing each element from the start. Such assembly is called a standard cell. Usually, these standard cells are gathered to form a so-called standard cell library utilized by designers. Statistically, in IC design, more than 90% of an intellectual property element is expressed by frequently-used standard cells. Thus, standard cells are very common in an intellectual property element library (IP library). Particularly, IP means originally “intellectual property,” however in semiconductor industry, IP is extended to a designed and verified integrated circuit design with specific functions, which is also called silicon intellectual property. Besides, since elements of an integrated circuit are very numerous and their connection lines are further complicated, the elements cannot be connected one by one manually and usually are done in accordance with layout algorithm by a design software. Thus, these complicated connection lines must be passed over when modifying the circuit design. Since adding new connection lines is more difficult than cutting original connection lines, the following descriptions are focused on adding new connection lines.
Please refer to FIG. 2 again, the integrated circuit standard cell of this embodiment includes four metal layers: the first metal layer 21, the second metal layer 22, the third metal layer 23, and the fourth metal layer 24. Usually layout of a standard cell only utilizes the first metal layer 21, but X node 11 may be connected to Y node 12 based on requirements of circuit correction or design modifying. However, the first metal layer 21 and the second metal layer 22 has already been used by other connection lines 41 and 42 so that nodes 11 and 12 cannot be directly connected and should be connected by way of other metal layers. Because the third metal layer 23 is also used by connection line 43, the connection is achieved by finding paths upwardly and downwardly. Please note that, in the embodiment, connection between X node 11 and Y node 12 blocked by connection lines is depicted schematically. Actually, connection lines distributed in the first metal layer 21 and the second metal layer 22 are very complicated such that X node 11 and Y node 12 cannot be connected directly.
Thus, each metal layer may be used to achieve the connection between X node 11 and Y node 12. At circuit design stage, a connection line should starts from X node of the first metal layer 21, then passes the second metal layer 22 and the third metal layer 23, and pulls back to the second metal layer so as to connect with Y node of the first metal layer. However, at actual production stage, connection lines of an integrated circuit should be modified by changing masks. Besides, since metal layers are insulated with each other, an isolation layer must be punched through to form a so-called via. By such design, there are five masks, including the first metal layer 21, the via 51 between the first metal layer 21 and the second metal layer 22, the second metal layer 22, the via 52 between the second metal layer 22 and the third metal layer 23, and the third metal layer 23, must being changed. And, the expense of foundry is based on the number of changed masks. Usually, the expense of changing a mask is NT$ 500,000. For the case of the above embodiment, merely adding such a connection line should change five masks and pay NT$ 2,500,000! It is a very astonishing cost. Further, it takes time to re-design layout and re-produce connection line masks. Thus, a new method should be found to reduce the cost of research, development and time for increasing competitiveness.